Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
JK Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Negative Edge
Polarity
Inverting, Non-Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
16
Set/Reset
Yes
Number of Elements per Chip
2
Maximum Propagation Delay Time @ Maximum CL
7.1 ns @ 2.7 V
Maximum Operating Supply Voltage
3.6 V
Dimensions
9.9 x 3.91 x 1.58mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
9.9mm
Width
3.91mm
Minimum Operating Supply Voltage
1.65 V
Minimum Operating Temperature
-40 °C
Height
1.58mm
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22
74LVC Family
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P.O.A.
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P.O.A.
10
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
JK Type
Input Type
Single Ended
Output Signal Type
Differential
Triggering Type
Negative Edge
Polarity
Inverting, Non-Inverting
Mounting Type
Surface Mount
Package Type
SOIC
Pin Count
16
Set/Reset
Yes
Number of Elements per Chip
2
Maximum Propagation Delay Time @ Maximum CL
7.1 ns @ 2.7 V
Maximum Operating Supply Voltage
3.6 V
Dimensions
9.9 x 3.91 x 1.58mm
Maximum Operating Temperature
+85 °C
Propagation Delay Test Condition
50pF
Length
9.9mm
Width
3.91mm
Minimum Operating Supply Voltage
1.65 V
Minimum Operating Temperature
-40 °C
Height
1.58mm
Product details
74LVC Family Flip-Flops & Latches, Texas Instruments
Texas Instruments range of Flip-Flops and Latches from the 74LVC Family of Low-voltage CMOS Logic ICs. The 74LVC Family use silicon gate CMOS technology and is designed to operate at 3.3V, allowing a significant reduction in power consumption when compared to 5V systems.
Operating Voltage: 1.65 to 3.6V
5V tolerant inputs
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 250 mA per JESD 17
ESD protection exceeds JESD 22