Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer
Number of Channels
1
Schmitt Trigger Input
Yes
Input Type
Single Ended
Output Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOT-553
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
11 ns @ 15 pF
Maximum Operating Supply Voltage
5.5 V
Dimensions
1.7 x 1.3 x 0.55mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
15pF
Minimum Operating Temperature
-40 °C
Height
0.55mm
Width
1.3mm
Maximum Operating Temperature
+85 °C
Length
1.7mm
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
Stock information temporarily unavailable.
Please check again later.
P.O.A.
20
P.O.A.
20
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer
Number of Channels
1
Schmitt Trigger Input
Yes
Input Type
Single Ended
Output Type
Single Ended
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SOT-553
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
11 ns @ 15 pF
Maximum Operating Supply Voltage
5.5 V
Dimensions
1.7 x 1.3 x 0.55mm
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
15pF
Minimum Operating Temperature
-40 °C
Height
0.55mm
Width
1.3mm
Maximum Operating Temperature
+85 °C
Length
1.7mm
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22