Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Line Driver
Number of Channels per Chip
1
Input Type
Single Ended
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
4.5 ns @ 3.3 V
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22
74LVC Family
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P.O.A.
25
P.O.A.
25
Technical Document
Specifications
Brand
Texas InstrumentsLogic Family
LVC
Logic Function
Buffer, Line Driver
Number of Channels per Chip
1
Input Type
Single Ended
Output Type
3 State
Polarity
Non-Inverting
Mounting Type
Surface Mount
Package Type
SC-70
Pin Count
5
Maximum High Level Output Current
-32mA
Maximum Low Level Output Current
32mA
Maximum Propagation Delay Time @ Maximum CL
4.5 ns @ 3.3 V
Dimensions
2 x 1.25 x 0.9mm
Maximum Operating Supply Voltage
5.5 V
Minimum Operating Supply Voltage
1.65 V
Propagation Delay Test Condition
50pF
Product details
74LVC1G Family, Texas Instruments
Low-Voltage CMOS logic
Single gate package
Operating Voltage: 1.65 to 5.5 V
Compatibility: Input LVTTL/TTL, Output LVCMOS
Latch-up performance exceeds 100 mA per JESD 78 Class II
ESD protection exceeds JESD 22